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Study of Double Stacked Si3N4 (SONNOS) Flash Memory based on Ultra-Thin Body Poly-Si Junctionless FET with Trench Structure
Thesis

Study of Double Stacked Si3N4 (SONNOS) Flash Memory based on Ultra-Thin Body Poly-Si Junctionless FET with Trench Structure

Wang, Wei Cheng
Masters, 國立清華大學, 工程與系統科學系
2014

Abstract

雙層氮化矽 溝槽式 超薄複晶矽通道 快閃記憶體 Double Stacked Si3N4 Ultra-Thin Body Junctionless FET Trench Structure
In this study, the “Double Stacked Si3N4 Flash Memory Based on Ultra-Thin Body Poly-Si Junctionless FET with trench structure”, the characteristics of transistor were improved by ultra-thin channel, and the double stacked Si3N4 was used to improve the poor retention ability of conventional SONOS memory device. Moreover, the fabrication has the simple process and compatible with current Flash memory process. Therefore, it has more opportunity to apply for high density 3D stack technology. In the point of transistor character, the device has excellent electrical performance, and the part of memory device which was used the double stacked Si3N4 layers as trapping layers that improving the memory characteristics. By FN-tunneling, the SONNOS device present better and higher yield than conventional SONOS device。 Beside, In the reliability of memory device, the SONNOS device also has excellent performance。Especially, the retention characteristic of SONNOS memory device has excellent performance under ten years at 85°C. The device memory windows maintain almost 99% no matter n-channel, p-channel, planar, or Nanowires structure.

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