Abstract
This work is the first time to demonstrate the gate-all-around (GAA) n-channel junctionless (JL) polycrystalline silicon (poly-Si) thin-film-transistor (TFT) with 2 nm ultra-thin channel. Using low temperature poly-Si (LTPS) to fabricate JL-GAA TFTs with ultra-thin channel are successfully fabricated by oxidation thinning process. This work use the dry oxidation to form the ultra-thin channel instead of directly depositing the thin-film as the poly-Si channel in JL TFTs. The dry oxidation thinning method could get larger grain size and less grain boundary than directly depositing the thin-film. The sub-threshold swing (SS) is 61mV/decade, and the on/off current ratio is close to 108 due to the excellent gate controllability and ultra-thin channel. The JL-GAA TFTs have a low DIBL value of 6mV/V, indicating greater suppression of the short channel effect than in JL-Planar TFTs. The cumulative distribution of electrical parameters in JL-GAA is small. Therefore, the proposed JL-GAA TFTs of excellent device characteristics along with simple fabrication are highly promising for future (system-on-panel) SOP and system-on-chip (SOC) applications. This process is simple and compatible with existing CMOS processes. Firstly, this work focuses on the device process and basic device characteristics analysis. Next, the reliability analysis of JL-GAA TFT include high temperature performance, breakdown mechanism and hot carrier stress are investigated in this thesis. In the high temperature reliability analysis, the JL-GAA TFT with ultra-thin channel indicates three characteristics: 1) The threshold volt-age (Vth) is less sensitive to temperature due to thinner channel thickness. 2) The subthreshold slope (SS) is nearly close to the idea values with increasing temperature due to the poly-Si channel approaching to single crystal. 3) The OFF-state current is lowest as temperature rises, owing to quantum confinement effect. In the high voltage breakdown mechanism analysis, the breakdown voltage (VBD) and breakdown mechanism of JL poly-Si TFT were compared to the conventional inversion-mode (IM) TFT using fabricated devices and 3D quantum hydrodynamic transport device simulation. The JL TFT shows excellent breakdown characteristics, the off-state VBD of 53.4V is several times larger than VBD of 9.5V in IM TFT with same device size. JL devices have large potential for high voltage power MOS devices and circuits application. The analysis of electric field distributions in on-state show that the channel of JL devices can equally share the voltage like a resistor, because there are no junctions formed between channel and source/drain. In the hot carrier stress analysis, the degradation behaviors after hot-carrier stress of JL-GAA, JL-Planar, IM-GAA and IM-Planar poly-Si TFTs are investigated. JL-Planar device presents better reliability than IM-Planar device after hot carrier stress. The lesser degradation is due to the peaks of lateral electric field of junctionless device is lower than inversion mode device. In this study, we demonstrate that JL-GAA TFT with 2nm ultra-thin channel shows excellent electrical characteristics. And we find that the threshold voltage of JL-GAA TFT is less sensitive to temperature, the breakdown voltage in JL-GAA TFT is several times larger than IM-GAA TFT and JL-Planar presents better reliability than IM-Planar after hot carrier stress.