Abstract
As the feature size of logic device has been scaled continuously, conventional inversion-mode Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) face a lot of challenges such as random dopant fluctuation, physical limitation and short channel effect (SCE). Junctionless FET is the one solution key in the future devices. JL-FET is a novel device, which has heavily doping channel with the same type to that of source and drain. Therefore, JL-FET has a nearly negligible drain-induced barrier lowering (DIBL), a slight short channel effect (SCE) and less thermal budget in process of fabrication. Because of the high concentration of dopants in channel, using a fully-depleted to turn off JL-FET is necessary. Ultra-thin body (UTB) have been employed to solve those problems. In this work, we adopt reactive ion etch (RIE) to form the polycrystalline silicon (poly-Si) UTB instead of directly depositing the thin-film as the poly-Si in JL-FET. The RIE thinning process could get larger grain size and less grain boundary than directly depositing the thin-film. After RIE thinning process, the nanowires look like the trench structure and the raise S/D structure is completed at the same time. In addition, gate-all-around (GAA) structure combine with UTB could improve gate control ability, that improve sub-threshold swing (SS) and reduce OFF-state leakage current. This work is the first time to demonstrate the GAA p-channel JL poly-Si transistor with 0.65-nm ultra-thin body. Using low temperature poly-Si to fabricate GAA trench JL-FET with ultra-thin body are successfully fabricated. The sub-threshold swing (SS) of GAA trench JL-FET is 60mV/decade, and the ON/OFF current ratio exceeds 109 because of the excellent gate control ability, ultra-thin body and raise S/D structure. The GAA trench JL-FET has a negligible DIBL value of 0.4mV/V, indicating great suppression of the short channel effect. Firstly, this work focuses on the device process, basic device characteristics analysis, device simulation and temperature performance. In simulation, we use Sentaurus TCAD to analyze the physical and electrical results. And the band-to-band tunneling (BTBT) will take place at the channel/drain junction region. This mechanism result in the GAA trench JL-FET with low SS.