Abstract
Modern electronic devices become more and more useful, emphasizing on multifunctional, small size, light weight, etc. The rapid development in electronic industries has led to considerable increases in consumer’s purchasing desire, and triggered electronics industry to improve its products. However, the expectation of transistors in scaling suffered more and more difficult to design, whether the short channel effect in devices or the challenge of process are very important research issues. In this thesis, the hybrid junctionless field-effect-transistors with trench structure are proposed and fabricated; the special fabrication of junctionless is the same doping concentration and doping type in channel, source, and drain, so the channel to source and the channel to drain have no junction. And these devices can avoid the short channel effects and simplify the fabrication compared to inversion mode transistors. The hybrid structure makes the thinner effective channel thickness owing to the depletion layer by the channel and substrate; it can easily fabricate devices on the bulk Si wafer and keep the good electrical characteristics. Then, the trench structure improves the ability of gate control owing to the thin channel by the anisotropic etching process. In the fabrication, the annealing after depositing the thick amorphous silicon gets the larger poly silicon grain size, and it also can improve the active area film quality; finally, it achieves the thin trench channel by the reactive-ion etching process. The hybrid poly silicon channel junctionless field-effect-transistors with trench structure have ten nanowires with omega gate structure. The performance of the hybrid junctionless field-effect-transistors with trench structure is excellent with the small sub-threshold swing (SS) (109mV/dec.), the high current ratio (Ion/Ioff current ratio > 108), and negligible DIBL (9mV/V); then, discuss the electrical characteristics in variable temperature with every 25oC as a step from the 25oC to 200oC, analyze those devices by using the Arrhenius sweeps. Finally, the last result shows the TCAD simulation to assist the analysis and confirms the measured basic electric characteristics. The proposed hybrid JL-FETs with trench structure not only the easy fabrication but also the good characteristics are highly promising for use in advanced system-on-chip and 3D stacked ICs applications.