Abstract
On-chip spiral inductor is one important component of RFIC, and suffers from low quality factor which is a figure of merit for performance comparison. There are many factors that affect the quality factor of spiral inductor, and one of the critical factors is the substrate effects. Consequently, understanding the behavior of on-ship spiral inductors on PD (partially depleted) SOI is a necessary step before designing a SOI RFIC. Four design parameters of spiral inductors and four different substrates were studied in this research by adopting a statistical method – Design of Experiment (DOE). Number of turns has most significant effect on the performance of an inductor, and is followed by inner diameter, spacing, and width. Inductor on high resistive wafer has better performance than it on low resistive wafer because the currents induced in the substrate are reduced. The impact of SOI wafers is minor to the performance of an inductor because small displacement current and small eddy current are induced in the thin silicon layer. High resistive SOI wafer will provide better performance for planar spiral inductors, and it is also IC compatible. By applying Taguchi method, maximum quality factor at 2.4GHz was predicted and verified to be 14.2, but the maximum quality factor over 0.1GHz to 20.1GHz is not as expected.