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Study of SONOS Nonvolatile Memory with Double Stacked Si3N4 Trapping layer and Nanowires Gate-All-Around Structure
Thesis

Study of SONOS Nonvolatile Memory with Double Stacked Si3N4 Trapping layer and Nanowires Gate-All-Around Structure

Chiang, Yi Wei
Masters, 國立清華大學, 工程與系統科學系
2015

Abstract

雙堆疊氮化矽 環繞式閘極 非揮發性記憶體 double stacked silicon nitride gate all around nonvolatile memory
In this study, the “SONOS Nonvolatile Memory with Double Stacked Nitride Trapping layer and Nanowires Gate-All-Around Structure”, the characteristics of memory are improved by oxidation trimming nanowires and doubled stacked silicon nitride fabrications. Compared with conventional SONOS fabrications, these fabrications enhance the threshold voltage shift, program/erase speed, reliability......etc. Moreover, they are simple process, low cost and suitable for 3C stack memory technology. In the thesis, we demonstrate how we fabricate the GAA SONOS device, and cross section of the device. After the measurement, we find that GAA SONOS NVM either operate in FN program or channel hot injection, but FN program shows better reliability. We also discuss and explain some memory effects and characteristics by TCAD simulation. We simulate the physical and electrical characteristics of the GAA SONOS and find out that they have a consistent trend. By the TCAD simulation result, we further know the distribution of the trapped electrons and holes, and then we explain how these phenomena affect our NVM devices.

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