Abstract
In this study, we describe the fabrication of a trench junctionless poly-Si field-effect transistor (trench JL-FET) with 2.4 nm ultra-thin channels. The dry etching process is utilized firstly in the fabrication of trench JL-FET is used to form a trench and define the channel thickness (TCH) and the gate length (LG) simultaneously. The trench structure was successfully and easily integrated into the JL-FET device. This work use the dry etching to form the ultra-thin channel instead of directly depositing the thin-film as the poly-Si channel in JL FETs and it could get larger grain size and less grain boundary than directly depositing the thin-film. The trench JL-FET has superior SS value about 100 mV dec-1, high ION/IOFF ratio up to 107 and practically negligible DIBL value. To confirm the stable process of trench and potential of advanced CMOS process, we have shown the trench JL-FET with different channel width and gate length. In this study of characteristics analysis, we firstly focus on detail fabricating process and typical electrical characteristics. It’s compare the trench JL-FETs (TCH=2.4nm) with the conventional JL-FETs (TCH=2.4nm). It’s worth to be mentioned that the saturation currents of trench JL-FETs are higher than that of conventional JL-FETs, owing to quantum confinement effect (QCE) in ultra-thin channel. The quantum confinement effect can improve the carrier mobility and electron velocity which is confirmed by TCAD simulation. Next, this work had shown the reliability analysis including high temperature performance and high voltage breakdown mechanism. This study investigated the temperature dependence on ID-VG curves of trench JL-FETs and conventional JL-FETs. The VTH and SS of trench JL-FETs are less sensitive to temperature than that of conventional JL-FETs that maybe due to the single crystal-like channel and fully-depleted state in the ultra-thin channel. Additionally, The trench JL-FET devices exhibit extremely small leakage currents as increasing temperature due to the energy subbands of quantum confinement effect. Finally, the breakdown mechanisms of JL-FETs and inversion mode (IM) FETs with different gate bias condition (on-state and off-state) are discussed completely and confirmed by experimental and simulated results. The simulated results show the maximum electric field of JL-FET is smaller than IM-FET, so the measured breakdown voltage (VBD) of JL device is 73V which is better than that of IM device. the trench JL-FET has a great potential for using in advanced AMLCD, 3D stacked applications, low power consumption applications, system-on-panel and high voltage power MOS devices.