Abstract
In recreant years, the electronic products pursue not only the higher speed and better performance, but also less power consumption and lower cost. The Semiconductor ICs manufacturing companies still follow Moore's law to scaling. In addition to processing technology feasibility limits, it is important to develop a target that suffices high performance and scalability. Information processing technology is driving the semiconductor into a broadening spectrum of new applications according to 2015 ITRS 2.0 report. A significant part of the research to further improve device performance is presently concentrated on III-V materials and Ge. These materials promise higher mobility than Si devices. The combination of 3D device architecture and low power device will usher the Era of Scaling, identified in short as “3D Power Scaling”. In order to increase transistor density for continuing Moore’s law, we implement the stacked nanosheert (NS) vertically inversion-mode field-effect-transistors(VM-FET) in 3D stacked integrated circuit (IC) applications. This research which focus on is showing the following: (1) device process, (2).basic device characteristics analysis, (3) device simulation. There are three kinds device structure. The first one is stacked Fin-FET, The second is stacked Gate all around VM-FET, The third is p-Channel Silicon/Germanium Quantum Well Multi-Gate Field-Effect-Transistor, we adopt the oxidation trimming method to form thin active layer and exhibit quasi-crystal channel due to the reduction of grain boundaries and defects. It is beneficial for excellent electrical performance. In the basic device characteristics analysis. First part will show the comparison of stacked Fin-FET and conventional stacked planar Fin-FET. The stacked Fin-FET exhibits the better performance. After that comparison of stacked Fin-FET and stacked GAA-FET. The stacked GAA-FET achieves lowing subthreshold swing (S.S.) and Off current. Second part will discuss about the change of width dimension for I-V characteristics with stacked structure. However, in the device simulation, we use Sentaurus TCAD to analyze and confirm the measured basic electrical characteristics. In our proposed the stacked NS VM-FET has better electrical characteristics. Moreover, it may provide a probable next-generation CMOS device solution and be utilized in advanced 3D stacked IC applications.