Abstract
Power dissipation in clock network distribution is one of the major sources of total power dissipation on a chip. In order to increase utility of the products, low-power techniques become very important, especially for clock network construction. Clock gating is an efficient way of reducing dynamic power consumption in digital circuits. It reduces switched capacitance by turning off transitions on a clock tree when the triggered registers do not need to change their values. Besides, bounded-skew clock tree is proposed to shorten the total wirelength of a clock net, implying lower power dissipation. Our work in this thesis is to construct a minimal power gated clock tree by integrating these two schemes. First, we propose a topology generation method to generate the clock tree topology with minimal output net loading. Second, we apply the bounded-skew clock routing algorithm to embed the generated topology. Finally, we perform buffer sizing by a dynamic programming approach to further optimize the power dissipation. The experimental results show that the algorithm is effective in reducing dynamic power consumption.