Abstract
Power consumption is critical in mobile electronic devices. The power consumption saving could be achieved while minimizing the performance degradation by means of Dynamic Frequency and Voltage Scaling (DVFS) technique. In modern computer, the power consumed by DRAM system takes a large portion of total power. Different from the traditional frequency scaling, in this work we propose to scale the DRAM voltage at the expense of the read/write latency. Beginning with the observation that the performance degradation in low voltage would be lower with low rank request intensity or high bank interleave, we quantify the two request characteristics and propose a rank-based dynamic voltage switching policy and the corresponding DV-DRAM controller. To evaluate the proposed switching policy, we build a full system platform, which integrates MARSSx86, DRAM simulator, and the DRAM Timing, Area, and Power, Modeling Tool named DArT. Compared among different benchmarks, the proposed voltage scaling policy improves the performance-power efficiency product (η) the most for the benchmark with low bandwidth due to low request intensity (39.3% power efficiency improvement for 2.1% performance degradation). For overall system performance, the proposed policy out-performs the static low or high voltage of the DV-DRAM when the system performance is weighted to the fifth power and the power-efficiency to the first power. We conclude that the proposed dynamic voltage scaling technique provides an intermediate choice for power and performance trade-off and improves the overall DRAM system performance under the defined evaluation condition. As an interface of the DRAM to the CPU, the proposed DV-DRAM high-level controller links the CPU simulator and the DRAM architectural-level modeling tool, DArT. These simulators together provide a system-level performance and power evaluation platform for various future system design candidates.