Abstract
Recently, keeping Moore’s law is more difficult because of the limitations of the process. Through-silicon via (TSV) based three dimensional integrated circuit (3D IC) is a popular way to meet the law. Thanks to the shorter vertical interconnection paths in 3D IC, its performance can be better than other packages or stacking technologies. There are many methods to stack dies together, e.g., wafer-to-wafer (W2W), die-to-wafer (D2W), and die-to-die stacking (D2D). In this work, without loss of generality, we assume the D2W stacking process is adopted. Moreover, memory is the most important product in semiconductors, and thanks to the rapid growth of data communication and smart handheld devices, the requirement of semiconductor memory is also growing. Recently, three dimensional DRAM (such as Wide-IO, Wide-IO2, HBM, etc.) which utilizes TSVs as the vertical paths to communicate between dies is considered as a good approach to achieving higher bandwidth and larger capacity. However, new defects can be introduced during the extra steps in manufacturing the 3D DRAM. Each added step may introduce its own type of new defects, reducing the overall yield. To prevent dramatic yield loss, the 3D DRAM may need to be tested before and/or after TSV fabrication. This work focuses on the TSV fabrication process, which is part of the entire wafer fabrication, packaging and testing flow for 3D-IC products. We analyze the test data from automatic test equipment (ATE) by spatial and temporal analysis. We separate the TSV array into several regions, and try to find the trend of misalignment by comparing the yields of these regions. In addition, we group failed TSVs which are close to each other. This work can get 92.392% in total detection accuracy, and 99.9843% for random failure, 97.2268% for cluster failure, and 79.8066% for misalignment.