Abstract
Test cost and test accuracy are the issues that must be considered in the stage of testing. Many dies can be integrated into single chip with the advancement of integrated circuit fabrication technology, but it makes the testing face stern challenges. Because the speed of chip increases too fast such that some chips can not be tested at operation frequency, it will raise the possibility of time-related faults. The higher density and greater amount of pads make the manufacture of probe cards more difficult and more expensive than past. HOY wireless test concept was proposed recently. It provides the improved test method due to plenty problems of traditional test. HOY concept is that test data are transmitted to DUT by using wireless communication technology. Therefore, the issues of pad density and pad size can be solved. Besides, the advantages such as improving test frequency and reduced test time etc. make the HOY wireless test attractive. This thesis proposes the cost model by modifying the model in bibliography based on HOY concept. The proposed model is constructed for most of ASIC without BIST and it can estimate three types of test methods: traditional test, wireless test without ID, and wireless test with ID. Moreover, only the I/O signals are transmitted wirelessly and the power and clocks are still transmitted though the probe cards. After estimation, HOY wireless test method can save test cost enormously. In addition, the maximum number of parallel tests for wireless test is larger than that for traditional test, so the test time of wireless test is shorter than that of traditional test. That means that a wireless ATE can test more dies and obtain more profit.