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Test Cost Reduction Methodology for Integrated Fan-Out Wafer Level Chip Scale Package
Thesis

Test Cost Reduction Methodology for Integrated Fan-Out Wafer Level Chip Scale Package

Wang, Kai Li
Masters, 國立清華大學, 電機工程學系
2015

Abstract

三維晶片 成本模型 整合扇出晶圓級晶片尺寸封裝 測試成本分析 晶圓測試 晶圓探測 3D IC cost model InFO WLCSP test cost analysis wafer test wafer probe
The integrated fan-out wafer level chip scale packaging (InFO WLCSP) is one of the emerging packaging technologies to achieving small chip form factor with low manufacturing cost. In InFO WLCSP, copper (Cu) pillars are used as the contact interfaces, which can be probed directly without solder caps, thus decreasing test cost. Without solder caps, however, Cu pillars that are exposed in the air will be oxidized gradually, which increases the contact resistance, and leads to test quality loss. To alleviate this problem, the touch-down is a scheme to remove oxidation which comes from contact interface. Thus, increasing the number of touch-downs (NTD) is usually used in the industry, which deals with oxidation effect efficiently, i.e., probing more times, can help penetrate the oxide layers. However, increasing NTD may damage the device under test (DUT), so there is a limit for NTD to prevent yield loss. Moreover, with an increased NTD, there is a higher chance for the probe tips to get attached by particles, and increases the contact resistance again. To alleviate this issue, polishing the tips to remove the attached particles is a commonly used mechanism. Increasing the number of polish (NP) is often adopted to maintain the test quality. As NP increases, however, a longer probing time is required, thus increasing the test cost. In addition, increasing NP shortens the remaining lifetime of probes. To reduce the test time, a number of sites (dies) can be concurrently tested by a probe card, which is denoted as NS. Increasing NS can reduce test time, but it also increases the probe card cost, so an optimal value needs to be identified. It therefore is clear that an optimization methodology should be developed, based on these competing parameters, in order to reduce the probing cost while maintaining the test quality. In this work, we develop a cost model to analyze the cost with respect to NTD, NP, and NS. With the proposed cost model, cost-effective probing configurations and procedures can be found effectively. Experimental results from an industrial case show that as much as 40.63% of the cost can be saved with NS = 5, NTD = 2, and the probe tips are polished after every 3 dies are probed.

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