Abstract
The advent of deep-submicron semiconductor technology makes system-on-chip (SOC) possible. In order to handle the complexity of design methodology, intellectual property (IP) reuse is broadly adopted. However, the reuse of IP cores leads to challenges in test integration. Additionally, the focus on stuck-at fault coverage is insufficient for the nanometer age, since many defects affecting the performance of circuitry are unintentionally ignored. Therefore, at-speed (performance) testing needs more consideration in test integration of SOC. We have proposed a Test Access Control System (TACS) targeting the test integration issues in SOC where IEEE P1500 Test Wrappers, a flexible test access mechanism (TAM), and the associated test controller are developed for stuck-at-fault testing. In order to consider the timing issues in SOC testing, we enhance our TACS with the ability of at-speed testing. Our TACS can apply not only the test patterns for stuck-at faults but also for timing-related defects. For example, the transition-fault test patterns generated by commercial tools can be translated automatically to the system level through our SOC Test Aid Console (STEAC) and applied to the embedded cores with timing requirements by our pin-efficient TACS Controller. Wrapper Boundary Register cells for delay test are chosen in our TACS architecture. The test circuitry insertion, test pattern translation and test scheduling are all operated automatically. We have applied this test platform to a SOC design of crypto processor, and the experimental results demonstrate our approach to be simple and efficient—low test integration cost, short total test time, and small area overhead.