Abstract
System-on-chip (SOC) design methodology is becoming a trend in IC industry. To reduce the time-to-market cost, SOC designs usually are composed of reusable cores from multiple resources. Although the manufacturing process of SOC and system-on-board (SOB) is similar, the SOC is much different from the SOB so far as testing is concerned. One of the major difference is test access and isolation. To make core test plug-and-play, the IEEE P1500 standard is being proposed. The standard is trying to standardize the Test Wrapper between a core and its host such that the core can be accessed or isolated in test mode. In this thesis, we propose an automatic framework for wrapping a core with P1500 wrapper. Different types of wrapper cells are designed, including high-performance, low-area, and bi-directional cells. Automatic wrapper generator and pattern converter are also presented. The wrapper generator can generates a wrapper with Verilog format and a test bench for verifying the wrapper according to the specified I/Os information of the wrapped core. The pattern converter can translate the core test into the wrapped core test. This is helpful for the users to reuse the core test rapidly. A SOC test chip which has four wrapped cores is implemented based on the proposed wrapper cells and generator.