Abstract
Trench gate MOSFET has recently played an important role in power devices because of its superior channel density compared to the planar MOSFET. But the process of trench reactive ion etching (RIE ) is an important issue because of the bombardment of energetic-ion. The RIE will strongly affect the micro-roughness of the oxide-silicon interface. Therefore, to improve the following gate oxide quality by reducing the trench etching damage is an important topic. Following the trench RIE process, several unit-step trench sidewall cleaning treatments including CF4 / O2 plasma etching, dilute HF solution dip, and sacrificial oxide annealing by N2O ambience were applied to remove the silicon damage and to optimize the electron transport. In order to probe into the mechanism and the effects of the post etching treatments described above, various conditions were designed in this experiment. We will observe the relations between device electric property and post etching treatments by monitoring the TZDB and TDDB performance in Chapter 2. Besides, DC (Static) and AC (Dynamic) oxide stress were used to investigate the degradation of device parameters in Chapter 3. Further, trench channel mobility extraction under low electric field of device post stress was also studied in Chapter 4 to characterize the trench MOSFET reliability and to optimize the post RIE treatment.