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The study of Charge Trap Flash Memory Device with band engineered trapping layer
Thesis

The study of Charge Trap Flash Memory Device with band engineered trapping layer

蔡政育
Masters, 國立清華大學, 工程與系統科學系
2009

Abstract

flash band engineered trapping layer
1.Improvement of P/E speed for NAN structure trapping layer higher charge tunneling efficiency lower Ig 2.Trapped charge detrap easier for HfO2 compared with Si3N4,but that’s a trade-off : erasing speed □ retention 3.Improvement of endurance characteristics for NAN structure compared with single Si3N4 trapping layer barrier oxide(Al2O3) reduces the trap generation during cycling 4.Simultaneous improvement in P/E speed and retention for Si3N4/Al2O3/HfO2 structure

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