Abstract
Three-dimensional (3-D) memory stacking like Hybrid Memory Cube (HMC) can resolve memory bandwidth challenges for multi-core system where stacked multiple DRAM dies are connected by Through Silicon Vias (TSVs). However, high power density due to the high in- tegration incurs temperature related problems in reliability, performance, and system cooling cost. In addition to thermal issues, in multi-core system, memory interference between pro- cesses may degrade system performance. In order to achieve better performance, we propose a dynamic page allocation policy considering access frequency of pages, physical locations of DRAM dies, thermal impacts, bandwidth variation of each process, and memory interference among processes. We also propose an analytical model to estimate the system performance considering the above factors. Experimental results show that our proposed memory mapping policy can outperform MCP [1] 12.7% on average. The average error rate of our analytical model is only 0.86%.