Abstract
As device scaling, the leading edge technology is moving to FinFET process. In order to improve the FinFET performance, the thesis focuses on the study of High-k/metal gate process. There are three parts in this work to discuss the effects of High-k/metal gate process on device characteristics. In the first study, Vth tuning by the PMA process after MG-1 gate stack is investigated. The EWF, Vth, and other electrical characteristics are discussed. It is found that there are two mechanisms affecting the work function value during the PMA process. First, Work function (WF) could be lower by M1 diffusion. Second, work function could be higher by dipole formation. Therefore, the Vth can be modified by the PMA process. PMA X+100℃ is the best annealing condition for MG-1 gate stack, which shows the best electrical performance. In the second study, Vth tuning by different metal alloys (MG-2 vs. MG-1) is studied. （MG-1：Metal A and Metal C，MG-2：Metal B and Metal C） The thermal stability and electrical characteristics of two different metal alloys are discussed with the same PMA process. The results indicate that the thermal stability of Metal B is worse than that of Metal A. For MG-2 gate stack, PMA X℃ is the best annealing condition which shows good performance. For FinFET process, MG-1 as metal gate stack is better than MG-2. In the last study, O2 PDA at low temperature and low partial pressure are implemented; in order to passivate oxygen vacancy in High-k. The variation of Vth and Ion, CET, other electrical characteristics and reliability are discussed. The results show that CET of O2 PDA is a little higher than that of STD. For PFinFET, most device performance can be improved. Lower Vth variation is obtained, which indicates the oxygen vacancy can be passivated. However, the improvement of device performance (Vth, σVth, Ion) for NFinFET is not achieved. For NFinFET and PFinFET, the reliability can be improved by O2 PDA.