Abstract
Three Dimensional Integrated Circuits (3D-ICs) are currently being developed to improve existing 2D designs by providing smaller chip areas, higher performance and lower power consumption. With the short and dense Through-Silicon-Vias (TSVs), multiple dies can be integrated to overcome the barrier of interconnection. However, before 3D-ICs become a viable technology, the understanding of 3D testing issues is still insufficient and there are still many unresolved testing challenges. To ensure the stack yield of future adopting of 3D-SICs, pre-bond testing is needed to provide the known good die (KGD). Since the TSVs are not fully accessible prior to bonding, testing the combinational logic between the scan flip-flops and TSV becomes a complex issue. In order to overcome the limitation of TSV, additional wrapper cells was proposed to be added at the two ends of TSVs to provide controllability and observability. Even though it is a major breakthrough for pre-bond testing, the wrapper cells used by the TSVs lead to significant area overhead and decrease the system performance. For reducing the number of additional wrapper cells, several approaches have proposed solutions by reusing the existing primary inputs/outputs or scan flip-flops to achieve high testability. However, practical timing considerations were overlooked and the number of inserted wrapper cells was still high. In this work, based on the previous work, we modify its algorithm to produce more number of re-used scan flip-flops. Moreover, by considering practical timing and layout information, our approach does not incur any timing violation. Furthermore, with the help of commercial ATPG tool, the re-usability of scan flip-flops can be maximized. Results are presented for 3D-stack implementations of the ITC’99 benchmark circuits.