Abstract
Routability estimation has become much more challenging for modern VLSI layout design. In this thesis a new approach for track assignment is presented, which utilizes global routing information to estimate routability in a more accurate manner. It first uses a greedy method to generate an initial solution, and then applies a negotiation-based rip-up and re-assignment method to improve the result. Di erent from any prior work, the proposed approach takes local nets into account and allows the generation of routing violations. In this way, the routing congestion information is not only more accurate than global routing but also closer to detailed routing. Experimental results are shown to support the robustness of the proposed approach.