Abstract
Transistor sizing is a timing optimization technique. We solve the transistor sizing problem by using a non-linear programming method with the SPICE Data Extracted Delay Model. The experiment result shows that the SPICE data extracted delay model is more precise than a simple RC or the Elmore delay model. The approach we proposed in this paper sized each transistor in the circuit twice at most. It is better than other approaches, such as convex programming and simulated annealing. It is because that the circuit characteristics of different circuits are much different. The parameters of the cost function could be modified in order to meet the circuit characteristics.