Abstract
The requirements of non-volatile memories for handheld consumer electronics, medical electronics, car electronics, and lots of electronic products become larger and larger, especially for large capacity, low cost, low power and high speed memory. After integrated with micro controller unit (MCU), it can effectively increase the chip performance. Flash memory is the mainstream embedded memory. However, it cannot achieve high speed write operation and be randomly accessed. Furthermore, it is difficult to scale down flash memory into deep nanometer scale. Thus, developing new nonvolatile memories is necessary. Among these emerging nonvolatile memories, Resistive Random Access Memory (ReRAM) is one of the most promising candidates. It has attractive characteristics such as low write power, small area, and logic-process compatibility which can lower the manufacturing cost. Currently, the most common memory cell structure is one transistor and one ReRAM (1T1R), which is suitable for high speed and low supply voltage embedded applications, particularly for devices powered by batteries. As devices shrink, ReRAMs have higher cell resistance (R) and greater variations in write time and R, which reduces the R-ratio (RH/RL) between the high-R state (HRS, RH) and low-R state (LRS, RL). ReRAM also has a high RL, which enables a larger voltage drop across ReRAM to reduce write voltage and cell-switch (CS) size. Thus, ReRAM memory macro designs suffer two major problems： 1. Small sensing margin (SM), limited read-VDDMIN, and slow access time (TAC) due to high-RL and small R-ratio. 2. Increase in energy due to large set DC-current (IDC-SET) resulting from wide set-time (TSET) distribution. Here, we propose swing-sample-and-couple voltage mode sense amplifier (SSC-VSA) and self-boost-write-termination (SBWT) scheme to solve above two major problems, respectively. Proposed SSC-VSA designs the VREF on specific voltage level, after the operation of the circuit, it can increase the usage of ΔVBLS_MIN (by up to 99%) as the SM for lower read VDDMIN and faster TAC. It can achieve 1.7x faster TAC across various VDD compared to conventional differential-input (CD) voltage mode sense amplifier. As for ReRAM write operation, proposed SBWT scheme is a 4T self-detective write-termination circuit. When ReRAM successfully sets (HRS→LRS), large IDC-SET will increase the BL voltage, enabling the positive feedback between BL and SBWT and cutting off the current path, which can save over 99% write power. We fabricated a 28nm 1Mb ReRAM memory macro. Under the 0.85V and 0.27V supply voltage, the measured read access times are 6.8ns and 404.4ns, respectively. Besides, the SBWT scheme has also been demonstrated.