Abstract
In our livelihood, the Static Random Access Memory (SRAM) appears in the almost electronics and it is required more area than other circuits in the SOC chip. That shows the SRAM used up the most power of a chip. So, how to solve the problem of SRAM power consumption and not to cut down the SRAM operating performance is a big challenge. The point about all problems of SRAM for reducing the power consumption is to lower the SRAM operating voltage. But, pulling down the operating voltage that made the static noise margin (SNM) of SRAM cell characteristics be smaller. This phenomenon will to cause the read half-selected disturb problem and write half-selected disturb problem when SRAM macro operating in write mode or read mode in the ultra low voltage. If SRAM macro happens the disturb problem which made the write fail or read fail, that is no meaning for to operate at ultra low voltage. In this work, we proposed a differential read write back sense amplifier (DRWB-SA) to cancel the write half-selected disturb problem of SRAM cell. This DRWB-SA will help the SRAM to operate at the ultra low voltage. And, we analysis the SA layout style about 1 dimension or 2 dimension common-centroid and one-pitch or two-pitch to reduce the SA offset, which is made DRWB-SA can success operating at ultra low voltage by small bit line (BL) swing. To test and verify, we proposed a 64kb SRAM macro with DRWB-SA that is used two-pitch common-centroid layout is fabricated in 90nm CMOS technology. By oscilloscope and CIC 93K tester to get measurement results of the 64kb SRAM macro, that can operate down to 230mV running at 1.3MHz. Benefiting from operation at 230mV, the operating power of SRAM is 15.36uW and 32.47pJ in energy consumption.