Abstract
Full-search motion estimation is a key component on video compression to efficiently remove temporal redundancy between successive frames, however it spends huge amount of computations thus it is unlikely to satisfy the real time requirement directly. Several speed up approaches have been proposed, either adopt some fast search algorithms or rely on specific hardware implementations. H.264/AVC is the latest video standard proposed by ITU-T VCEG, which is more flexible and efficient on motion compensation than those found in earlier standards. One new feature introduced by H.264/AVC standard about motion estimation is to support multiple possible block sizes (16x16, 8x8 and 4x4) for motion estimation within a macroblock of size 16x16. This indicates that much larger numbers of motion estimation would be produced than before, thus better effective hardware designs should be investigated nowadays. Conventional hardware architectures can be categorized as three classes: one-dimensional array, two-dimensional array and tree architecture. In this thesis, several effective hardware architectures for fulfilling H.264/AVC variable block size motion estimation are proposed. Besides, computation-aware techniques for computation saving as well as power consumption are considered also.