Abstract
Traditional standard cell placement algorithms assume that all standard cells are the same height that they can be aligned to placement rows. However, with the increasing complexity of VLSI technology, multiple-row height cell becomes more common which leads to a new challenge. Pervious works treat multiple-row height cell as movable macros that will waste a lot of time or even cannot get a legal solution. In practice, standard cells have power rail on the top or bottom side. Therefore, they must be aligned to proper rows that they can be powered. In this thesis, we propose a double-row height placement algorithm considering power line alignment constraint. First, we cluster cells to triple-row height then we treat three consecutive rows as one row. Conventional placement algorithm can be applied. Second, if there are cells do not satisfy power line alignment constraint, we just swap it with its clustered cell or move it up/down one row to solve this problem. Eventually, the refinement will further improve wirelength. The result shows we just get 2.6% worse wirelength compared to [12] while they do not consider power line alignment constraint.