Abstract
With the continuous down scaling of the technology, the performance and levels of CMOS VLSI circuit has been on a tremendous boost over the past decades. However, device scaling, power supply lowering, and frequency increasing of operation that accompany with the technology progress will induce the reliability problem. In modern digital integrated circuit, adaptive voltage scaling is regarded to be the most efficient way to achieve low power design and which can also make a design more robust. However adopting this low power technique to the digital circuit is difficult in engineering practice at design stage. In digital system design, cell-based methodology is regarded to be the most popular design flow in the various customized IC design market. Based on this fact, we proposed a simple cell optimization flow to develop a cell library which enables a low voltage operation under nominal value. Meanwhile, voltage scaling technique can be adopted to the modified cell-based design flow. By adding the adaptive detect circuitry, the voltage value of the system will be adjusted to its optimal point. By the error detection signal report at runtime, we can observe the system correctness and make a more robust design. Finally, a test circuit is implemented under TSMC 0.18um 1P6M CMOS process. And it shows a dynamic voltage system will have almost 50% power saving comparing to the full margin design.