Abstract
Reducing power is an important issue in modern core-based SOC designs. Using multiple supply voltages on a SoC design is an efficient way to achieve low power. However, it may lead to a complex power network and a huge number of level shifters if we just set the cores to operate at their respective lowest voltage levels. We present two formulations for the voltage level assignment problem. The first is exact but takes longer time to compute a solution. The second can be solved much faster with virtually no loss on optimality. In addition, we propose a modification to the traditional floorplanning framework. Unlike previous works, we can optimize the total power consumption, the level shifter overhead, and the power network complexity without compromising the wirelength and the chip area. In the experiments, we obtained 17- 53\% power savings with voltage island generation.