Abstract
Sequential layered integration technology that can fabricate 3D sequentially stacked CMOS low thermal budget process (<450oC) is proposed in this article. With green laser crystallized epi-like Si, chemical mechanical polish (CMP), and surface modification processes for thin channel fabrication, 3D stackable 50nm node ultra-thin body (T_Si=14nm) n/p-MOSFETs with steep subthreshold swings (88 and 121 mV/dec.) and high on-currents (121 and 62 μA/μm) are demonstrated. Not only the transfer characteristics are better than the devices without CMP thinning processes (T_Si=50nm) but they are less sensitive to the temperature. Therefore, we can find that the large-grained laser crystallized channel (grain size~1000nm), followed by a novel super-CMP- planarization process (reducing the mean roughness from 37A to 5A) play a core technology in this thesis, and the other properties of film are identified by Raman and XRD diffraction pattern. In order to solve high contact resistance which will reduces drive current (Ion) of device as feature size keeps scaling, we proposed the structure with embedded Source and Drain (e-S/D) to increases the thickness of source and drain region to reduce contact resistance. In this structure, the drive currents have improvements of 20 to 30% compared to the device without e-S/D. Finally, we combine this structure with independent back gate (BG), V_th adjusters for 3D sequential integrated circuit are also realized by low thermal budget process. With additional back gate structure, UTB devices can offer flexible controllability in threshold voltage (V_th) with large γ (body factor>0.05) even though the W_Fin of channel is shrunk to 20nm, and we can also get larger body factor by changing the material of back gate with low resistance. Thanks to the quantum confinement effect, such V_th adjustable nanowire devices perform well at higher temperatures, which give a wide design window for 3D sequential integrated circuit.