Abstract
Today, there are many communication system uses orthogonal frequency division multiplexing (OFDM) and the most important things is its sensitivity to synchronization problems. The synchronization errors are included time and frequency parts and they will due to inter symbol interference (ISI) and inter carrier interference (ICI). For these reasons, symbol timing synchronization and carrier frequency offset compensation are the key functions .In this thesis, these functions are discussed in AWGN channel and fading channels on implemented architecture. The architecture is implemented on FPGA and reports in this thesis. Besides these problems, the FFT processor is the most speed critical part in the OFDM communication systems. In these systems, low power is usually one of the major concerns. We propose a memory based recursive FFT design in FPGA for the low power base-band OFDM transmitter and receiver for WiMax (Wireless Metropolitan Area Network) application. It is implemented by radix-8 FFT. As results, the power consumption will be reduced by 28% compared to radix-4 FFT [2]. The proposed architecture has three advantages: (1) fewer butterfly iterations to reduce power consumption, (2) pipeline of radix-8 butterfly to speed up clock frequency, (3) even distribution of memory access to make the best utilization efficiency of SRAM ports.