Abstract
Clock networks have a great influence on the performance and the characteristic of VLSI designs. Since a large portion of power is dissipated on clock networks in a chip, researchers pay much attention to power reduction techniques for the clock network. Clock gating is an effective power reduction technique for sequential circuits. In this work, we propose a zero-skew gated clock network construction algorithm for a given clock tree topology. It considers the locations and the activity patterns of clock sinks to build up the clock tree by a bottom-up phase and a top-down phase extended from the Deferred-Merge Embedding (DME) algorithm. Our algorithm does not restrict every root-to-leaf path to have equal number of buffer/masking-gate stages. The flexibility of buffer and masking gate insertion leads to a wider exploration of the solution space for a design. The experimental results show that our approaches gain 7% - 12% improvements on power saving against the previous clock gating methods.