Abstract
For microprocessor-based embedded systems, instruction fetching and decoding usually contribute a large percentage of system power. In addition, the frequencies of the instruction types to be used usually have uneven distribution. Based on the observation, the instruction decoder can be partitioned into small groups for power minimization. In this thesis, we have proposed an effective hMetis-based partitioning algorithm to minimize the power consumption for an instruction control-signal decoder. We use hMetis [10] to be our partitioning kernel, and then model the input file of hMetis from instruction-execution sequence. The fix file is further introduced into hMetis for power minimization. We successfully combine the architecture proposed in [3] with hMetis partitioning program. The results show that the 4-way hMetis-based partitioning has generated the best result with 47.02% power reduction, 50.22% timing reduction with 49.47% area overhead. For the 3-way hMetis-based partitioning, we obtain 48.86% power reduction, 12.34% timing reduction with only 37.93% area overhead.