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一個600億赫茲寬調變範圍鎖相迴路
Thesis

一個600億赫茲寬調變範圍鎖相迴路

黃俊維
Masters, 國立清華大學, 電機工程學系
2011

Abstract

57~64 GHz鎖相迴路 頻率合成器 振盪器 除頻器 57~64 GHz PLL Frequency synthesizer Oscillator Divider
With the advances in semiconductor process, the band of the wireless communication system gradually increased, the local oscillator output frequency in the transceiver of the communication system also will improve, This paper presents a center frequency of 60 GHz in the ISM band, 57 ~ 64 GHz wide tuning range lock loop. The second chapter introduces the basic operation of the phase-locked loop principle, neutron circuit for the circuit one by one, the tear down the loop transfer function and phase noise of mathematical models. Chapter three of this paper of 57 to 64 GHz wide tuning range lock like a loop structure, the first on the circuit parameters of the proposed framework using Matlab to do simulation and verification, including the phase margin, noise analysis, the loop is locked analog, and for each block in the phase-locked loop circuit architecture, the input reference frequency of 25 MHz in the charge pump current, VCO, injection locked frequency divider are adjustable role of phase-locked loop with broadband the role of the voltage-controlled oscillator injection locking in addition to the frequency of the frequency modulation principle described, then explore and explain the phenomenon of non-ideal circuit behavior and seek to improve to enhance the performance of phase-locked loop. The fourth chapter concerns focus on the circuit structure of the simulation, the simulation and verification of a single block, the entire phase-locked loop to do the simulation, including the loop is locked, the phase noise simulation; use TSMC 65nm process off the assembly line, and finally attached to the circuit layout illustration.

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