Abstract
In this paper we propose a highly efficient timed model for pipelined out-of-order processors based on resource usage analysis. Existing timed processor models either are limited to simple processor architectures or are inefficient for system simulation purpose as they require detailed micro-architecture analysis. By capturing the timing of resource availability changes in the proposed instruction-oriented simulation algorithm, the cycle counts of programs executed on the target processors can be accurately and efficiently computed. The experimental results show excellent performance scalability and accuracy of the proposed instruction-oriented approach for processor architecture explorations. For processor models with increased cycle counts, the proposed approach incurs four times less overhead than the CA approach.