Abstract
在本篇論文中我們提出了一個包含測試設計考量的三伏特680 MHz鎖相迴 路.此鎖相迴路主要是提供在高速操作下的微處理器一個精確的週期信號. 此鎖相迴路包括有:一個三級的壓控振盪器,除頻器,相位頻率偵測器,電荷 充放電器,以及低通濾波器. 壓控振盪器的主要功用是 產生一個週期性的振盪信號,而其振盪週期則是隨輸入的控制電壓而改變, 除頻器是降低壓控振盪器的頻率為原來的十六分之一. 相位頻率偵測器是 偵測外部參考頻率及除頻器輸出的相位與頻率差異.電荷充放電器是將相 位頻率偵測器的數位輸出信號轉換成控制壓控振盪器頻率的類比信號. 低 通濾波器則是過濾掉電荷充放電器的高頻輸出信號. 我們用一個鎖定信號 來決定是否鎖相迴路是在鎖定頻率及相位的狀態.我們也利用兩種錯誤模 型來測試鎖相迴路. In this thesis, we present a 3V 680 MHz phase-locked loop (PLL) with testable design which can be used in a high speed microprocessor. This PLL consists of a three- stage differential voltage-controlled oscillator, four divide-by-2 frequency dividers, a phase frequency detector, a charge pump, and a loop filter. The proposed voltage-controlled oscillator is a three-stage differential oscillator. The output frequency range of this voltage-controlled oscillator which is suitable for advanced microprocessors is from 530 MHz to 680 MHz. The free running frequency is about 600 MHz. The divide-by-2 frequency divider used here is a true single phase D-FF. Because of its circuit simplicity, it is fast and small. The phase frequency detector compares the phase of two input signals and produces the control signals to the charge pump. The purpose of the charge pump and the loop filter is to convert the logic states of the phase frequency detector into analog signals suitable for the controlling the voltage-controlled oscillator. The loop filter is a first-order RC low pass filter. We also take the testing of the PLL into consideration. We apply two fault models to our PLL and we use a lock signal to indicate whether the PLL is in the lock state. The PLL is designed with the UMC 0.5um DPDM CMOS technology. The maximum power consumption is 88mW at 680MHz. HSPICE post-layout simulation results justify the feasibility of our proposed PLL.