Abstract
Abstract Department：Electrical Engineering Title：A Timing Circuitry of UWB Impulse Radar Achieving 1.5ps Time Resolution over 100ns Advisor：Prof. Ta-shun Chu Graduate student：101061594 Li-Wei Jheng In today's wireless technology as we know, whether Bluetooth or Wi-Fi, and so on, the main subjects of the developing application are limited to the bandwidth, making many large capacity and high-quality information and files cannot be fast transferred. The ultra-wideband technology is the key to solve the current application of short-range transmission of information. Ultra-wideband technology has developed not short of time in the past, especially in the military field. Such as radar can be used to detect UFO or unknown object underground, such as mines, in order to protect the safety of personnel and so on. The advantage of ultra-wideband technology is small size, low power consumption, and low cost, so if imported ultra wideband technology into livelihood purposes is very suitable presumably, it will bring more convenience to people's lives. In this thesis, to make ultra-wideband impulse radar can have a better time resolution, we proposed and implemented a timing circuitry combines phase-locked loops and shift registers, making the ultra-wideband impulse radar can achieve 1.5ps time resolution over 100ns. It contains three phase-locked loops, one to ensure the synchronization of the transmitter and receiver radar signal, the other two are used to implement the timing circuitry. Timing circuitry is mainly constituted by shift registers, it divided into two parts, one part for the coarse-tune circuit, the other for the fine-tune circuit. We do it is to prevent to use too much shift registers which will led to the circuit does not work. Transmitter and receiver signal after the shift register will generate multiple signals of different phases, and finally we need to use the MUX select transmitter and receiver signal compared to calculate the distance from both ends. This Thesis is divided into five chapters, the first chapter is the motivation and Introduction, the second chapter is phase-locked loop architecture, and internal sub-circuit architectures and principles of operation, the third chapter is the timing circuitry structure and principle of operation that we have proposed, chapter IV is the simulation results, and we’ll make some discussions, and the fifth chapter is summary.