Abstract
Squaring is a special case of multiplication. Traditionally, squaring can be performed by using multiplier itself with the same inputs for saving area or a squarer. Squaring circuit forms the heart of different DSP operations such as Image Compression, Decoding, Demodulation, Adaptive Filtering, Least Mean Squaring etc. As the applications evolved and the demand for the high speed processing increased, squaring function and dedicated squarers are implemented. Initially, squaring is performed by using Look Up Table (LUT) approach if delay is primary concern with the penalty of area. Major drawback of this LUT scheme is large area, which increases exponentially as the number of input bits increases. Due to the cost and the interconnect delay, this approach is not the most preferred implementation. A lot of researches have been conducted in order to develop different methodologies to implement squarer, giving more importance to improve delay and to reduce area constraints. This research modifies Karatsuba squarer for using an improved algorithm and alternative logic testing. The proposed testable Karstsuba squarer can be applied in the circuit under 50% utilization rate and 100% fault coverage of single stuck-at fault model with the penalties of area increased (n^2+454n-264)/(56n^2-96n+40)×100% and delay (n+2)/(4n-4)×100%. Take n=64 for instance, the area and delay increase 14.73% and 26.19%, respectively. The proposed algorithm can reduce Area of (9n+50)/(92n-14 )×100%(transistor count). For example, the area saved is 10.65% for n=64.