Abstract
Excessive power dissipation in integrated circuits causes overheating and can lead to soft errors or permanent damage. The problem is even more severe as the level of integration increases. Therefore, accurate and efficient power estimationis important in a design process. Transistor-level power simulators, which are more accurate than logic-level power estimators, have been popularly used for CMOS logic design. In this thesis, we propose a fine-grained mixed-level approach for power estimation. The approach combines the efficiency of logic simulation and the accuracy of transistor-level simulation. In this approach, there are two phases - power modeling and power extrapolation. In the power modeling phase, we partition the circuit into several blocks and run logic simulation and low-level simulation with random patterns. Then, we calculate each block's relationship factor ( multiple alpha ) of the circuit instead of the original relationship factor ( single alpha ) of the total circuit. In the power extrapolation, we run low-level simulation with functionalpatterns. Then, we use each block's relationship factor pre-calcuated in the power modeling phase and each block's average toggle count due to these functional patterns to approximate the total power dissipation. Experimental results show that the fine-grained modeling ( using multiple alpha ) is better than a coarse-grained one modeling ( using single alpha ). On the average of the power estimation error is improved by an order from 7.3% to 0.65%.