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一個對H.264中全文自適應二進制算術編碼器的硬體架構設計
Thesis

一個對H.264中全文自適應二進制算術編碼器的硬體架構設計

劉普昇
Masters, 國立清華大學, 資訊工程學系
2005

Abstract

全文自適應 CABAC
We propose a full hardware implementation of Context-Based Adaptive Binary Arithmetic Encoder. Our architecture includes a 14-way context pair generator composed of binarization and context modeling, a 3-stage pipelined circuit for getting neighboring data and a 3-mode 4-stage pipelined arithmetic encoder with forwarding logic for context update. Our arithmetic encoder architecture can process one bin per cycle. The whole encoder is able to process 0.77 bins per cycle on the average.

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