Abstract
In recent years, the design on bio-medical electronics has been getting more emphasized, especially the relative application on mobile device or portable monitors for the on time bio-signal acquitsition system. Low power consumption and high hardware efficiency are the trend of the requirement of portable devices. A 0.5-V 10-bit, 1.28MS/s successive approximation register analog-to-digital converter (SAR ADC) for the acquisition system of bio-medical signals is presented in this thesis. A capacitor switching detection circuit mainly constructed by two auxiliary comparators is applied to determine whether the high weighted capacitor in DAC should join the switching process or not for different input voltage cases. Through this detection, the wasted switching power can be avoided and also promote the performance of SAR ADC. The SAR ADC is fabricated in TSMC 90nm CMOS technology, and it is 868μm × 868μm of area for whole chip and 260μm × 234μm for the core circuit. At 0.5V and 1.28MS/s, the post-layout simulation results of SAR ADC are DNL of 0.21/-0.30 LSB, INL of 0.28/-0.13 LSB, SFDR of 76.42 dB, SNDR of 61.54dB, ENOB of 9.93 bit, power dissipation of 3μW, and FOM of 2.4fJ/conversion-step. For experiment, it achieves DNL of 0.58/-0.43 LSB and INL of 0.84/-0.63 LSB, SFDR of 66.28dB, SNDR of 56.66dB, ENOB of 9.12 bit, power consumption of 3.86μW, and FOM of 5.59 fJ/conversion-step. In order to achieve better performance of SAR ADC, another 10-bit SAR ADC is presented and also fabricated in TSMC 90nm CMOS technology. The switching detect circuit is replaced by digital logic gates and lessen the analog circuit concerns such as matching and parastic capcaitors due to routing which induces from the two auxiliary comparators. The chip area are 868μm × 868μm for total and 238μm × 200μm for core circuit. At 0.5V and 1.28MS/s, its post-layout simulation DNL and INL results are DNL 0.20/-0.28 LSB、0.21/-0.16 LSB, respectively; SFDR of 79.06 dB, SNDR of 61.67 dB, ENOB of 9.95 bit, power dissipation of 3μW, and FOM of 2.36fJ/conversion-step. For experiment, it achieves DNL of 0.56/-0.59 LSB and INL of 0.57/-0.70 LSB, SFDR of 66.97dB, SNDR of 56.55 dB, ENOB of 9.1 bit, power consumption of 3 μW, and FOM of 4.38fJ/conversion-step.