Abstract
This thesis describes a Time of flight (ToF) technology with continuous wave modulation scheme applied in three domination (3D) CMOS imager sensors. Using integration signal equalization and sub-integration technology achieve noise cancellation and background light suppression (BLS) ability extension. A prototype 64×128 pixel imager employed these schemes experimentally achieve 67% fixed-pattern-noise (FPN), 300μV kTC noise cancelled and 30 fps in the 2D image mode. The imager implements two different pixels array compared between the image performances. The full chip system consists of their associated column parallel differential switched-capacitor OPAMP, S&H circuits, column and row decoders, enabling a pixel pitch of 10μm with nine transistors in a pixel, 24.8% fill factor in a TSMC 0.11μm CIS process, the chip size is 2.2mm×2.5mm. The innovations are contributed by this thesis, leading to the performance outlined above. First, a novel 4T in-pixel equalizer with reset noise cancellation (RNC) scheme which equal the signal after multiple integrated in two storage points. Compare to the 3T-like signal readout in conventional ToF imager which the integration points will be reset to the high voltage in the reset signal sample phase and therefore inject the thermal noise. The new technology cancels the reset noise caused by the reset MOSFET threshold variation and kTC noise. This operation improves the uniformity of imager at different exposure environments. The commonly readout circuits of the correlated double sampling (CDS) circuit can be omitted; in fact the CDS is pseudo operation in noise cancellation. Second, a sub-integration method for giving a wide dynamic range of background light suppressed ability. Third, the fully differential switched-capacitor OPAMP with sample and hold circuits are used in column-wise circuits for compensating the gain loss caused by the source follower in conventional active pixel sensors and reduced about 90% power consumption from the column shared OPAMP in the signal readout period, reaching good power efficiency.