Abstract
In recent years, people are increasingly more and more dependent on internet. With the advancement of science and technology, the methods of surfing on the internet turn from wire network to wireless network. When it comes to wireless internet in our daily life, people always associate Wi-Fi. The requirements of everyone can be satisfied by using wireless internet and it merely needs a small router AP. Therefore, it is a practical and challenging study subject that the integrated circuits can be applied to the circuit architecture of the Wi-Fi system. A delta-sigma phase locked loop with 2.8–4.8 GHz tuning range was proposed in this thesis. The main architecture of proposed PLL is divided in several parts, phase and frequency detector, charge pump, 3rd loop filter, multi-band voltage controlled oscillator, and a divider controlled by delta-sigma modulator. The non-ideal effect of charge pump was reduced by adding a unit gain buffer. The wide tuning range of voltage controlled oscillator was mainly due to six pairs of switched capacitors. The high enough resolution of divisor is fulfilled by 16-bit delta-sigma modulator. The entire architecture of proposed PLL was composed by the circuits mentioned above. In addition, the circuit of proposed PLL was fabricated using a 1P7M 55nm standard CMOS technology and the core circuit occupied an area of 0.32 mm2. The experiment results indicated the total power consumption is 24 mW at 1.2 V supply voltage, the theoretical resolution of the divisor is 1/65536, the range of operation frequency was divided in 64 bands, and the locked time was 1.25 μs. Besides, the comparison of three kinds of PLLs was as the beginning of this thesis, and the mathematical model of PLLs, the designed flow, the simulation results of proposed circuits, the considerations of measurement were described step by step. Finally, an integrated conclusion for the proposed PLL was given in the last chapter.