Abstract
In the military band, frequency of 35 GHz is commonly used in missile and radar systems. Additionally, In wireless communications, the use of an antenna array have a better SNR than a single antenna since each of the antennas in an antenna array at the receiver or transmitter can have a phase difference between the signals. We can achieve the purpose to enhance the SNR by referring the information to the back-end digital signal processing. This thesis presents a phase-locked loop with phase rotated function operating at 35 GHz . We joined a sub-injection architecture in VCO to reduce the phase noise of the oscillator itself. The first stage divider is using injection locking frequency divider. After underclocking, we give a set of orthogonal signal into two programmable gain amplifier(PGA). It can adjust the phase of the output signal by adjusting the gain of PGA and using some trigonometric function. Furthermore, the reference signal can be generated by pulse generator or another PLL which is equipped with delta-sigma modulation function. The latter can further increase phase noise performance. This paper is organized into five chapters, the first chapter introduces the research motivation and background; second chapter is the analysis of phase-locked loop structure, the internal operation of each sub-circuit principle,and some noise issues for discussion; the third chapter for this thesis presented with phase-locked loop with phase rotated function operating at 35 GHz be introduced, including the selection of the structure and the derivation of the application principle ;fourth chapter is to present the results of the simulation, and do some discuss; final chapter as a summary of the entire thesis to make a conclusion, and summarize the future outlook.