Abstract
For applications in the field of wireless communication, this thesis proposes A 8GHz Phase Locked loop with phase rotated function, the input reference frequency of 1GHz, through the phase locked loop will increase its output frequency to 8GHz, which is mainly used in antenna arrays, compared to a single antenna array antenna can get a better signal to noise ratio in, because the antenna array, each antenna when receiving or transmitting signals generated by the circuit can be controlled phase difference, and sent to the back-end digital signal processing control through these phase differences, to enhance the signal to-noise ratio, and achieve well-signal transmission / reception quality. In this thesis, the phase locked loop circuit using a first-order filter (Type-I PLL) architecture, which features unconditionally stable, and direct use of phase detector and loop filter composed of feed forward path, compared with conventional phase frequency detector coupled with a feedforward current path of the pump, the former has a better linearity, if the phase detector output is not linear, the noise will be fed directly into a control voltage of the voltage controlled oscillator, and thus phase investigation Linearity is measured becomes very important. In addition, this paper proposes an addition to the phase shift circuit through two b / c circuit, coupled delta-sigma modulator can be maintained at a fixed frequency, output phase adjustment phase locked loop, the delta-sigma modulator using ten two yuan input, loop bandwidth of the reference frequency of one per cent, on the grounds that to filter out the noise delta-sigma modulator caused. In Part reference signal source by quartz oscillator or an external signal generation source. In this thesis, we use 65nm CMOS process provided by TSMC,the thesis is divided into five chapters, the first chapter introduces the research motivation and background, and the second chapter focuses on the basic framework of analysis phase-locked loop, the sub-circuit The principle of operation and design proposed for the operation of the third chapter of the thesis adjustable function of varying phase locked loop design process to 8GHz equipment, including the choice of structure and principles of derivation, followed by the fourth chapter of the simulation results, and finally concluding chapter, and summarized future research goals and outlook.