Abstract
Before placement and routing of large circuits, floorplanning helps reducing the problem size. Most traditional floorplanners optimize chip area. However, circuit performance is very important nowadays. This study proposed a modified slicing floorplanner that can optimize timing. Simulated annealing is employed to explore the solution space. Our approach effectively checks the wire delay on critical paths and places bounded modules along the boundary. Experimental results indicate that our floorplanner reduces wire length and performs well in the test problems.