Abstract
Abstract(英文摘要) With the rapid development of technology, the transmission of information on the accuracy and speed requirements are more demanding for the mobile communication system, that the design of high-speed circuit architecture seems to have become a trend in contemporary society. Signal in nature are all continuous analog signals, but it is common to process data in digital signals, so between the analog and digital signals, we need an analog-to-digital converter to convert both signals, and the successive approximation register analog-to-digital converter is more widely used, this analog-to-digital converter without additional operation amplifier circuit architecture, relative to other analog-to-digital converter, it occupies less circuit area and has low power consumption advantage. This thesis implements a 150ms/s 10bits hybrid SAR ADC with time-domain analysis, the first four bits was generated by time domain analysis analog-to-digital converter, and the last six bits use traditional Vcm-based successive approximation register analog-to-digital converter to generate. This hybrid analog-to-digital converter reduce the number of switching times on capacitor and the compare times to comparator, that it can reduce power consumption effectively and save the switching time to achieve high-speed sampling frequency and low power consumption. The proposed ADC design in TSMC 65nm process, when input signal frequency is 0.44MHz, the signal to noise and distortion ratio is 57.15dB, the effective number of bits is 9.201bits, and the average power consumption is 3.513mW.