Abstract
A framework for embedded memory built-in self-test (BIST) compilation, called BRAINS (Bist for RAm IN Seconds), is proposed. According to the memory specifications and the test requirements, BRAINS generates the synthesizable BIST code in Verilog HDL, as well as its activation sequence, test bench and synthesis scripts. The architecture for BIST circuits generated by BRAINS is an improved version of our previous work. The new design provides at-speed testing, and programmable March tests. With the user's configuration, the generated BIST circuit can further provide bank interleaving access, diagnosis support, and be shared among multiple memory cores. BRAINS generates the BIST circuit by using the Memory Modeling Techniques. With the techniques, it is easy for BRAINS to support modern and customized memory architecutres. Two real industry chips for different SRAM architectures are shown as our experimental results. The area overheads are 3.5\% and 4.3\%, repectively.