Abstract
在本論文，我們提出了一個三伏、快速鎖扣，應用於高速系統之寬頻帶鎖 相迴路。此鎖相迴路為應用於資料/時脈回復時之頻率合成器。它是以電 荷充放電式鎖相迴路設計而成。此鎖相迴路包含數個元件—一個相位檢測 器、一個電荷充放電器、一個壓控振盪器、一個濾波器和一個除頻器。為 了達成快速鎖扣，相位檢測器是由相頻檢測器實現而成。此外，不同路徑 之延遲也列入設計考量以達到更高之工作頻率。藉由比較二輸入之相位和 頻率差，相頻檢測器，依此差異產生四個輸出。在相頻檢測器，後接一電 荷充放電器，其數位邏輯輸出可被轉換成一類比訊號，以達到控制壓控電 壓器之目的。此電荷充放電器具有一些優點，包括電流的相配和低電晶體 數，而由於此鎖相迴路需產生多相位輸出，我們使用五級之差動式壓控振 盪器來得到十個不同相位之輸出。由於是使用差動式，此振盪器具有較好 之雜訊抵抗力，此外，此振盪器還有全振幅及對控制電壓迅速反應之特性 。此鎖相迴路是以0.6微米，DPDM之CMOS製成，而由HSPICE之模擬結果可 證實此晶片之正確性。 In this thesis, we propose a 3V, fast lock-in phase-locked loop with wide frequency range for high speed data systems. This PLL, which is used as a frequency synthesizer for clock/data recovery, is realized by a charge-pump PLL. The PLL consists of several components, a phase detector, a charge pump, a voltage- controlled oscillator, a loop filter, and a frequency divider. For fast lock-in, the phase detector is implemented by a phase- frequency detector. Furthermore, path delay is taken into consideration for higher speed operation. By comparing the phase and frequency difference of it's inputs, the PFD generates four outputs in response to the difference. Then, accompanying the PFD by a charge-pump the four logic values are converted as an analog signal for controlling the voltage-controlled oscillator. The charge pump has the advantage of having current matching property and being as simple as 8 transistors only. Since the PLL is to generate multi-phase outputs, a 5-stafe differential VCO is used to generate 10 outputs. Since being differential, the VCO has better noise rejection.In addition, the VCO has the property of being nearly full-swing and sensitive to controlling voltage variation.The PLL is realized by 0.6 □m DPPM CMOS technology. The HSPICE post-layout simulation results justify the feasibility of out proposed PLL.