Abstract
Layout optimization problem of integrated circuit design become more and more important. As the IC industry moves toward deep sub-micron era, interconnection delay will more important then gate delays. Therefore, the interconnection delay in deep sub-micro can no longer be neglected. In this thesis, we present a structure-like method to perform performance-driven placement. Most electronic designs are described by hierarchical register-transfer schematics. Today, most electronic designs are described by hierarchical register-transfer schematics. In addition to gates, latches, and flip-flops, schematics include register-transfer components, such as register, counters, ALU’s, shifters, multiplexers, and macro-cells. These designs are usually described as a mixed RTL/logic/gate-level description in HDLs such as Verilog and VHDL. Ideally, an HDL design description is represented as a set of interconnected modules in a hierarchical way so that the design hierarchy can be preserved. However, when designers use HDLs to describe their design specifications and behaviors, the HDL design description is predominately by designers’ coding styles.