Abstract
In the cell-based design flow,iteraions are applied for correcting the timing violations,To reduce the number of iterations,we propose a new design flow with a hierarchical grouping floor plan and an editor for interactive grouping and placement.Our tol provides an environment for circuit grouping and floor planning.We also embed a critical-path weighted hierarchical floor-planning method to automatically place the grouped module. Experimental results have demonstrated that our propose method can reduce the wire length and timing delay of the critical paths.